This invention relates to methods and apparatus for detecting electrical defects in a semiconductor device or test structure having a plurality of features that are specifically designed to produce varying voltage potentials during a voltage contrast inspection. More particularly, it relates to voltage contrast techniques for detecting open and short type defects within the features of the circuit or test structure.
A voltage contrast inspection of a test structure is accomplished with a scanning electron microscope. The voltage contrast technique operates on the basis that potential differences in the various locations of a sample under examination cause differences in secondary electron emission intensities when the sample is the target of an electron beam. The potential state of the scanned area is acquired as a voltage contrast image such that a low potential portion of, for example, a wiring pattern might be displayed as bright (intensity of the secondary electron emission is high) and a high potential portion might be displayed as dark (lower intensity secondary electron emission). Alternatively, the system may be configured such that a low potential portion might be displayed as dark and a high potential portion might be displayed as bright.
A secondary electron detector is used to measure the intensity of the secondary electron emission that originates from the path swept by the scanning electron beam. Images may then be generated from these electron emissions. A defective portion can be identified from the potential state or appearance of the portion under inspection. The portion under inspection is typically designed to produce a particular potential and resulting brightness level in an image during the voltage contrast test. Hence, when the scanned portion's potential and resulting image appearance differs significantly from the expected result, the scanned portion is classified a defect.
Several inventive test structures designed by the present assignee are disclosed in co-pending U.S. patent application No. 09/648,380, entitled TEST STRUCTURES AND METHODS FOR INSPECTION OF SEMICONDUCTOR INTEGRATED CIRCUITS, filed 25 Aug. 2000, by Akella V. S. Satya et al., which application is incorporated herein by reference in its entirety. In one embodiment, a test structure is designed to have alternating high and low potential conductive lines during a voltage contrast inspection. In one inspection application, the low potential lines are at ground potential, while the high potential lines are at a floating potential. If a line that is meant to remain floating shorts to an adjacent grounded line, both lines will now produce a low potential during a voltage contrast inspection. If there is an open defect present within a line that is supposedly coupled to ground, this open will cause a portion of the line to be left at a floating potential to thereby produce a high potential during the voltage contrast inspection. Both open and short defects causes two adjacent lines to have a same potential during the voltage inspection.
Unfortunately, conventional voltage contrast test structures have associated disadvantages. For example, at least two photolithography masking steps are required to fabricate these test structures. One masking step is required for creating the contacts to the substrate, which is grounded, and another masking step is required for fabricating the metal layer of the test structure which is being tested. The time required to fabricate a conventional voltage contrast test structure could be important in some applications, such as using the voltage contrast based test structures for quickly qualifying and/or monitoring a process tool's status.
Another more significant deficiency of the conventional voltage contrast test structures is that they can only detect hard opens and shorts. This becomes an extremely significant issue, for example, in Cu metallization processing because a significant percentage of the defects are partial opens. These partial opens, in vias or in metal lines, are a reliability concern and also degrade the parametric performance of the semiconductor chip.
Accordingly, there is a need for improved test structures which may be quickly fabricated. Additionally, there is a need for improved test structures in which partial open and short defects may be detected.